1. Field of the Invention
The invention relates to a semiconductor memory device having a double-stacked capacitor structure and to methods for manfacturing the same, and more particularly to a semiconductor memory device having a double-stacked capacitor structure wherein one of the stacked capacitors is formed over and one is formed below a bit line and to methods for manufacturing the same.
2. Information Disclosure Statement
Generally, as the integration ratio of a semiconductor memory device increases, the unit area required for constituting the unit memory cell decreases and the capacity of the capacitor also decreases. Therefore, a semiconductor memory device not having a plate-type capacitor structure but rather having a trench-type capacitor structure or stacked-type capacitor structure has been developed, in order to enhance the capacity of the capacitor.
However, as the integration ratio of the semiconductor memory device increases greatly, the ability to obtain a highly-integrated memory device in a limited unit cell area of a single capacitor structure is limited.
In order to overcome such limitations, a multiple-stacked capacitor has been developed, which is disclosed in an article entitled "3-dimensional stacked capacitor for 16 mega byte and 64 mega byte DRAM", IEEE, 592-595 IEDM 88. As shown in FIG. 4, the multiple-stacked capacitor consists of a charge storage electrode 32 of a multiple layer which is connected to a source electrode 4 of MOSFETS. A bit line electrode 30 is formed below the plate of the charge storage electrode 32 and is connected to a drain electrode 4' of said MOSFETS. The drawing also shows a gate electrode 3, plate electrode 33, field oxide layer 2 and insulating layer 31.
However, under the above-mentioned prior art, there are difficulties in manufacturing the multiple-stacked structure capacitor, and the bit line contact or charge storage electrode contact of the stacked capacitor ceases or fails to be a proper contact due to a step occurring.
Therefore, it is an objective of-the present invention to solve the problems set forth above and to provide a semiconductor memory device having a double-stacked capacitor structure, having a first-stacked capacitor, and a bit line formed thereover, and a second-stacked capacitor formed over the bit line, and to provide methods for manufacturing the same.